1. Field of the Invention
The present invention relates to a drive circuit of a liquid crystal display (LCD), more particularly relates to a circuit for correcting deviation among channels, and to a liquid crystal display including such a drive circuit.
2. Description of the Related Art
In recent years, rapid advances have been made in display panels using a liquid crystal as a display.
This display panel is widely used for viewfinders and liquid crystal display panels of video camcoders, televisions for automobiles, display panels of navigation systems, and displays of notebook type personal computers etc.
Further, recently, television receivers of a rear projection type using liquid crystal panels, projectors for projecting a screen of a personal computer directly on a large screen without using an overhead projector, etc. have been spreading in use.
Further, there is also a movement for replacing the displays of desk top type personal computers conventionally using cathode ray tubes (CRTs) with liquid crystal panels so as to return desk space to the users and save on consumption of electric power.
Behind all of this has been the rise of the degree of precision and the improvement of the image quality (full color, high contrast, wide vision, compatibility with moving pictures, etc.) of the liquid crystal panels and the improvements in the peripheral technology (drive circuits, element technology, backlighting, and so on).
Thanks to the overall improvements in these technologies, liquid crystal display panels are now being used in a wide field of application.
In this regard, however, while the image quality of the newest display panels is becoming close to that of CRT displays, there are still a large number of areas requiring improvement.
As one of these, the drive circuit of the liquid crystal panel can be mentioned.
The drive circuit of a high precision and high image quality liquid crystal display panel is extremely large in size, requires a large number of chips, and requires high precision circuits. The required displayed image quality has therefore become one of the major factors preventing the display panels from being reduced in cost.
Below, problems in the drive circuits of liquid crystal display panels of the related art will be explained in detail using concrete examples.
Many types of liquid crystal elements exist. The panels enabling display of full colors and moving pictures are almost all of the so-called "thin film transistor" (TFT) type where thin film transistors are arranged at the individual liquid crystal elements constituting the pixels.
The circuit configuration of a cell forming a pixel of such a thin film transistor type liquid crystal display panel is shown in FIG. 19.
One end of an individual liquid crystal cell CC of a pixel of a thin film transistor type liquid crystal display panel is connected to a counter electrode EL as shown in FIG. 19. All of the cells of all of the pixels are commonly connected to this counter electrode EL. The other end is connected to a thin film transistor provided for each cell.
The thin film transistor is used as a switch, therefore, while there is inherently no distinction between the source and drain, for convenience's sake, here it is assumed that the source is connected to the liquid crystal cell CC. A gate of the thin film transistor is connected to a gate drive line GL. A line for writing pixel data is selected by a drive signal thereof. Further, the drain is connected to a data drive line DL to which is supplied the pixel data to be written into the individual liquid crystal cells of the selected line.
When the write operation to the selected line is ended, the thin film transistors of the line are turned off, but the voltage of the pixel data is held until the next write operation is carried out due to the capacitance of the liquid crystal cells CC and thin film transistors.
The configuration of the pixel cell of the thin film transistor type liquid crystal display panel shown in FIG. 19 is common to all panels.
On the other hand, there are several types of structures and methods of production of thin film transistors, methods of driving the counter electrodes, and methods of driving the pixel data. These will be organized and the overall situation and peripheral structures will be explained below.
The structures and processes for production of thin film transistors may be roughly classified into methods using amorphous silicon and methods using polycrystalline silicon.
The former do not require any high temperature process, so a large size panel using glass as a substrate is easily formed.
The latter involve a high temperature process, so require a quartz substrate and therefore have been limited to use for small sized panels heretofore. Recently, due to the advances in the technology of a laser annealing etc., the technology has been developed for forming polycrystalline silicon thin film transistors at a low temperature and it has become possible to manufacture medium sized panels of the polycrystalline silicon thin film transistor type.
The degree of mobility of the carriers in a polycrystalline silicon thin film transistor is larger than that in an amorphous silicon thin film transistor by about one order of magnitude. Accordingly, in the case of an amorphous thin film transistor, the ON resistance thereof is high, so a considerably long write time had to be taken.
Contrary to this, in the case of a polycrystalline silicon thin film transistor, the write time may be made considerably short. This results in a large difference in the configuration of the drive circuit of the gate.
FIG. 20 is a view of the system configuration of a liquid crystal display, showing also a drive circuit, in an amorphous thin film transistor type liquid crystal display panel.
In FIG. 20, reference numeral 10 denotes the liquid crystal display panel, and 20 an image data drive circuit.
In the liquid crystal display panel 10, m and n number of pixel cells PXC comprised of the liquid crystal cells and thin film transistors are arranged in a horizontal direction and a vertical direction. Terminals S and G of the pixel cells PXC are data drive signal terminals and gate drive signal terminals, respectively.
The pixel cells PXC arranged along the same horizontal direction line are connected to common gate drive lines GL1 to GLn, while these gate drive lines GL1 to GLn are connected to a gate line drive circuit 11. Further, the pixel cells PXC arranged along the same vertical direction column are connected to common data drive lines DL1 to DLm, while these data drive lines DL1 to DLm are connected to the image data drive circuit 20 via the pixel data drive terminal.
The gate line drive circuit 11 is basically constituted by a shift register and generates a line selection signal by a vertical synchronization signal VSYNC and a line clock LCLK.
Further, the image data drive circuit 20 comprises m number of latches 21-1 to 21-m and digital-to-analog converters (DACs) 22-1 to 22-m. The output of each is connected to the pixel data drive terminal of each column. The latches 21-1 to 21-m and the digital-to-analog converters 22-1 to 22-m convert the digital image data IMD supplied as serial data to one line's worth of parallel analog signals.
By such a configuration, in a period of a certain line of the pixel data (video signal) IMD, a predetermined line is selected by the gate line drive circuit and one line's worth of m number of pixel data is supplied in parallel to the pixel data drive terminals, whereby the pixel data is written into the pixels.
As the write time, substantially one line's worth of time, typically 10 to several tens of .mu.s, can be used. This makes it possible to ensure a sufficient write time even in an amorphous thin film transistor type liquid crystal display having a large ON resistance.
FIG. 21 is a view of another example of the configuration of the image data drive circuit.
This image data drive circuit 20a converts one line's worth of pixel data to parallel analog signals by sample-and-hold (SH) circuits 23-1 to 23-m and 24-1 to 24-m. In this case, the image data is supplied as analog signals. In order to convert serial signals to a parallel format, as shown in FIG. 21, two sample-and-hold circuits are necessary for each data line.
In an actual liquid crystal display panel, the number of pixels of one line, that is, the number m of the data lines DL, is equal to 640 in for example a VGA specification panel.
Recently, panels of larger numbers of pixels have become demanded. A greater number of pixels per line such as m=800 in the SVGA specification, m=1124 in the XGA specification, and m=1280 in the SXGA specification is now being required. Further, in the case of color displays, three times these numbers of pixels become necessary.
In this way, recent color liquid crystal display panels require image data drive circuits comprised of about 3000 channels of latches and digital-to-analog converters or sample and hole circuits (6000 circuits when counting sample-and-hold circuit elements). This in turn requires a large number of integrated circuits (ICs) with large numbers of pins and technology for forming the as many as 3000 interconnections between these integrated circuits and the liquid crystal panel. Further, to obtain a high image quality, it is necessary to ensure that these image data drive circuits all feature substantially the same characteristics.
Contrary to this, since a polycrystalline silicon thin film transistor has a small ON resistance, the write time can be greatly shortened.
For example, in a panel having a small number of pixels such as for a viewfinder of a video camcoder, as shown in FIG. 22, it is possible to construct almost all of the circuits on the liquid crystal display panel.
The liquid crystal display panel 10a shown in FIG. 22 sequentially selects data line switches DQ1 to DQm by a data line switch drive circuit 12 and fetches the image data into the data drive lines DL1 to DLm.
It is sufficient so far as the circuit for supplying the image data samples and holds the analog data and drives the liquid crystal panel by a signal in a form of a step wave. Since the thin film transistors of a large number of data line switches are connected to an input terminal of the image data of the liquid crystal panel, the input capacitance thereof is considerably large, so the circuit must be able to drive a large capacitance.
This type of configuration is only possible in panels of about 200,000 pixels in which several hundreds of ns are allocated to an ON time of the data line switches.
In a liquid crystal panel of the VGA specification having about twice this number of pixels and of the SVGA, XGA, and SXGA specifications having further larger numbers of pixels, even with polycrystalline silicon thin film transistors having a small ON resistance, the time allocated to the data line is too short and it is not possible to write signals into the data drive line by this method.
In this way, in a polycrystalline silicon thin film transistor type liquid crystal display panel having more than a certain number of pixels, the required write time is secured by not one input of image data, but by dividing the input into p number of channels.
As the number p of channels, 2, 3, 4, 6, 12, 24, etc. is used according to the number of pixels.
FIG. 23 is a view of the system configuration of a liquid crystal display including a liquid crystal display panel in the case where the input is divided into 2 channels.
In this liquid crystal display, the input to the liquid crystal display panel 10b is divided into an input 1 and an input 2, and the data is input in parallel. For this reason, two thin film transistors each of the data line switch are driven together such as DQ1/DQ2, DQ3/DQ4, and DQm-1/DQm.
This configuration corresponds to the configuration of FIG. 20 of the amorphous thin film transistor type liquid crystal display panel. Here, the image data is input as a digital signal.
Where the image data is supplied as an analog signal, as shown in FIG. 24, an image data drive circuit 20c may be constituted by a sample-and-hold circuit.
This configuration corresponds to the configuration of FIG. 21 of the amorphous thin film transistor type liquid crystal display panel. The sample-and-hold circuits 23-1, 24-1, and 25-1 and 23-2, 24-2, and 25-2 are constituted by three-stage cascade connections.
The reason why the three-stage configuration is adopted is that at least three stages are necessary in order to convert serial signals to p number of channels of parallel signals and output the same at the same timing and further to prevent the cascade connected sample-and-hold circuits in the channels from simultaneously entering into the sample mode.
If the sample-and-hold circuits were to operate ideally, in principle two stages would be sufficient, but in order to simultaneously output all channels, in at least one channel among the p number of channels, the initial stage sample-and-hold circuit and the next stage sample-and-hold circuit must simultaneously enter into the sample mode. Entry of vertical stripes into the displayed image as a result of a minute differences in characteristics between that channel and another channel due to this is therefore prevented.
The reason why there is no problem if there are two or more stages in the amorphous thin film transistor type liquid crystal display panel shown in FIG. 21 is that there is a blanking period between lines of the image data for convert one line's worth of signals to parallel signals, so a simultaneous sample mode can be avoided even with just two sample-and-hold circuits.
In this way, a polycrystalline silicon thin film transistor type liquid crystal display panel is characterized in that the image data drive circuit is greatly simplified in comparison with an amorphous thin film transistor type liquid crystal display panel.
Next, an explanation will be made of the fact that the applied voltage must be periodically inverted so as to drive the liquid crystal elements.
The optical characteristic of a liquid crystal element is determined by the absolute value of the applied voltage as shown in FIG. 25 and does not depend upon the polarity.
On the other hand, application of an electrical field in the same direction means that liquid crystal molecules are continuously twisted in the same direction. This becomes a cause of deterioration and image persistence. For this reason, the general practice is to invert the direction of the electrical field every predetermined period. The methods thereof may be roughly classified into the following two types.
A first method will be explained in relation to FIG. 26.
In this example, the voltage (counter electrode signal) VCOM of the counter electrode common to all cells of the liquid crystal elements is fixed to for example 7V. Signals supplied to the liquid crystal elements are inverted in a period A and a period B with the counter electrode signal VCOM as the axis of symmetry.
This inversion is carried out for example for every line, but the signals applied to the individual liquid crystal cells are inverted for every frame.
Next, a second method will be explained in relation to FIG. 27.
In this method, the counter electrode signal VCOM is also changed in the period A and the period B. The optical characteristic of a liquid crystal element is determined by a relative relationship of the drive signal to the counter electrode and the cell, therefore, FIG. 27 and FIG. 26 are equivalent for a liquid crystal element.
In this method, a new function of driving the counter electrode becomes necessary, but the amplitude of the video data when including the inversion operation becomes a half or less. Accordingly, this is convenient for realizing a lowering of voltage and lowering of power consumption of a video data drive circuit.
Above, a general explanation was given of the configuration of the thin film transistor type liquid crystal display and the drive method for the same. Next, an explanation will be given of the problem of deviation in characteristics in the image data drive circuit according to the present invention.
The number of channels of a image data drive circuit is from several hundreds to 1000 channels or more in the case of the amorphous thin film transistor type and about 2 to 12 channels in the case of the polycrystalline silicon thin film transistor type except for simple panels having small numbers of pixels.
In the case of color, further, three sets of these are necessary. When the characteristics of these channels are not well matched, a phenomenon occurs where only pixels of a certain column will be a little darker or brighter than those of other columns and vertical stripes will start to be observed. For this reason, the maximum deviation of channels, while depending also on the characteristics of the liquid crystal elements, is about .+-.10 mV. With this, the deviation is almost never able to be visually detected.
This is because, in the optical characteristic of the liquid crystal element shown in FIG. 25, when a tangent is drawn in an area in which the applied voltage and the transmission rate are linear, a dynamic range thereof is only about 1 to 2V. When considering that a detection limit of vertical stripes is about 1%, the dynamic range is about .+-.10 mV.
When the resolution of color is about 16 colors (4 bits) or 256 colors (8 bits), this problem is not that serious since the object of use is generally the display of text and graphic information.
However, recent display panels are provided with a display capability of 32,000 colors (15 bits), 260,000 colors (18 bits). and so-called "full color" 16,000,000 colors (24 bits) and therefore can display video information. Accordingly, very strict specifications are now being set for the deterioration of the image quality due to vertical stripes etc.
FIG. 28 is a view for explaining an input/output characteristic due to error. FIG. 28 assumes a case where a liquid crystal element is driven by 2 to 12V corresponding to the characteristic of FIG. 26.
In FIG. 28, a straight line indicated by &lt;1&gt; indicates the relationship of Vout=Vin in the specification.
A straight line indicated by &lt;2&gt; indicates an offset error. If there is only offset error, the allowable offset voltage is .+-.10 mV.
A straight line indicated by &lt;3&gt; indicates a gain error with which the error becomes zero when Vin=0. The precision of the gain required for guaranteeing an error of .+-.10 mV when Vin=12V is .+-.0.83%.
A straight line indicated by &lt;4&gt; indicates a gain error where adjustment is made so that the error becomes zero at the center (7V) of a required voltage range (2 to 12V). The precision of the gain required in this case is .+-.0.2%.
In this way, matching of characteristics among channels required for an image data drive circuit requires very strict specifications for both of the offset error and gain error.
An image data drive circuit is usually required to have the functions of a sample-and-hold circuit or digital-to-analog converter, an amplification circuit, and a buffer circuit.
First, for an overview, consider for example the circuit shown in FIG. 29. The transmission characteristic of this circuit is given by the following equation. Voff is an input conversion offset voltage of an operational amplifier AMP. EQU Vo=(1+R2/R1).multidot.(Vi+Voff) (1)
The error of the transmission characteristic of this circuit is determined by the input conversion offset voltage Voff and a relative difference of the resistance values of R1 and R2. In the case of a required specification of 10 mV, an offset voltage of the operational amplifier AMP sufficiently smaller than this can be realized if the device constituting the operational element is a bipolar type transistor.
In the case of a metal oxide semiconductor (MOS) type transistor, it is considerably difficult to hold the offset voltage sufficiently smaller than 10 mV.
As the relative precision of the resistance value, about .+-.1% can be guaranteed by suitably designing the pattern structure, but it is difficult to greatly exceed this.
Further, in a sample-and-hold circuit, the higher the operating speed, the easier offset occurs. This is because, for the high speed operation, the held capacitance value becomes small. Due to a parasitic capacitance etc. of the switching element, transfer of excess charges appears as the offset voltage at the time of a switching operation.
Next, an explanation will be given of a more concrete example of the related art for suppressing this deviation in characteristics among channels.
FIG. 30 is a view of a basic circuit of a complementary metal oxide semiconductor (CMOS) type digital-to-analog converter used in the image data drive circuit of an amorphous thin film transistor type liquid crystal display panel. In FIG. 30, an example of 8 bits is shown.
In this circuit, the minimum voltage Vmin and the maximum voltage Vmax are supplied from the outside, and 256 types of voltages with equipotential difference are generated by the resistors R1 to R255.
Only one transistor is selected from among the switch transistors Q1 to Q256 by a signal decoded from the fetched 8 bits of data. The voltage thereof is taken out at the digital-to-analog converter output.
In this circuit, since the MOS transistor is used just as a switch, if the voltage generated by resistance division is correct, no offset will be generated elsewhere. In order to avoid influence from the error of the resistor train, taps are provided in the middle of the resistor train.
In FIG. 30, taps Vc1 to Vcn are provided at 4 LSB intervals. By connecting the taps of the resistor trains of all circuits in parallel, the voltages of all circuits are forcibly made the same. By reducing the relative characteristic difference among circuits, a required inter-channel deviation is realized.
As apparent from the above explanation, in an amorphous thin film transistor type liquid crystal display panel, even in a VGA specification panel--the simplest for a display for a personal computer -, 1920 image data drive channels are necessary for a color panel.
One channel becomes one digital-to-analog converter based on the principle as shown in FIG. 30. About 200 to 300 of such digital-to-analog converters are integrated on one IC chip. Several of such ICs are therefore used to construct the image data drive circuit required for a display.
There are very few examples of actual use of an analog input amorphous thin film transistor type liquid crystal display panel using a sample-and-hold circuit as shown in FIG. 21. Almost all panels are of the digital-to-analog converter system as shown in FIG. 20. This is because it is very difficult to suppress the difference in characteristics among channels and therefore difficult to obtain a high image quality.
Accordingly, rather than the analog system of the simple circuit configuration using sample-and-hold circuits, the digital system using digital-to-analog converters, which is easier to obtain performance from even if the size of the circuit becomes extremely large, has been the mainstream.
Next, an explanation will be given of a image data drive circuit of a polycrystalline silicon thin film transistor type liquid crystal display panel of the related art.
Polycrystalline silicon thin film transistor type liquid crystal display panels have become practical only relatively recently. Due in part to this, the circuitry is still not as well established compared with the amorphous thin film transistor type. Of the two, the analog system using sample-and-hold circuits has been used more often.
The number of pixel data drive channels in a polycrystalline silicon thin film transistor type is a very small 2 to 24 or so (three times this in the case of color), but a high speed operation is required.
For this reason, in the digital system using digital-to-analog converters shown in FIG. 23, video signal use digital-to-analog converters are used. It is however again very difficult to guarantee a difference of characteristics of less than .+-.10 mV between video signal use digital-to-analog converters. For this reason, adjustment of the offset and gain is required. This is possible since the number of data drive channels of the polycrystalline silicon thin film transistor type is small. In the amorphous thin film transistor type, adjustment of channels is not practical.
In the analog system using sample-and-hold circuits, for example, the following steps may be taken.
First, by the concept of FIG. 29, the circuits are constituted so that as much as possible all circuits operate as voltage followers.
This is because if R2/R1 is made 0 in the above equation (1), the difference in characteristic becomes only the offset voltage and is no longer dependent upon the resistance ratio.
Accordingly, the sample-and-hold circuits and the buffer circuits are basically constituted so as to become voltage followers.
Further, a circuit for periodically inverting the drive signal to the liquid crystal elements is arranged at a stage before the sample-and-hold circuits. This circuit has a function of inverting the polarity of the signal and shifting the DC level, therefore, it is almost impossible to hold the error among circuits to within .+-.10 mV.
Accordingly, if a single circuit is inserted in common for all image signals before the signals are converted to serial signals, it becomes unnecessary to consider variation among circuits.
FIG. 31 shows a concrete example of the configuration of an image data drive circuit 30 of a polycrystalline silicon thin film transistor type liquid crystal display panel.
In this circuit, an image signal SIM is input to an amplifier AMP41 and an inverting amplifier AMP42 constituting the voltage follower.
Further, the output thereof is switched by a signal POL from a timing signal generation circuit 40 by a switch SW41. The output thereof is supplied to the sample-and-hold circuits 31-1 to 31-6 of six channels.
Each channel is constituted by three sample-and-hold circuits 31-1 to 33-1, 31-2 to 33-2, 31-3 to 33-3, 31-4 to 33-4, 31-5 to 33-5, and 31-6 to 33-6.
Outputs of the sample-and-hold circuits 33-1 to 33-6 are buffered by amplifiers AMP31 to AMP36 constituting voltage followers. The outputs thereof drive the pixel data drive terminals of the liquid crystal display panel.
Note that the timing signal generation circuit 40 also generates sample pulses SP1-1 to SP1-6, SP2-1 to SP2-3, and SP3 of these sample-and-hold circuits 31-1 to 33-1, 31-2 to 33-2, 31-3 to 33-3, 31-4 to 33-4, 31-5 to 33-5, and 31-6 to 33-6.
By such a design, the difference in characteristics between channels is relatively reduced, but it was difficult to keep this to within .+-.10 mV. Particularly, it is difficult to realize a low offset voltage characteristic in high speed sample-and-hold circuits.
The reason for this will be explained below.
FIG. 32 is a circuit diagram of a concrete example of the configuration of a sample-and-hold circuit.
This circuit is the sample-and-hold circuit most generally used in a bipolar type IC and is constituted by npn type transistors Q41 to Q47, resistors R41 and R42, a capacitor C41, and current sources I41 and I42.
SH and SHX indicate differential signals for switching the sample operation and the hold operation. When the signal SH is at "H (high level)" and the signal SHX is at "L (low level)", the mode is the sample mode, a current I1 flows through the transistor Q46, the transistors Q41 to Q44 and Q47 operate a s voltage followers, and the input VIN is transmitted to the output VOUT as it is.
When the signal SH is at "L" and the signal SHX is at "H", the mode becomes the hold mode, the transistors Q41 and Q42 are turned off, and the capacitor C41 holds the voltage immediately before this to thereby perform the hold operation. This circuit operates very Ideally in the case of a low speed sample-and-hold operation.
However, if it is intended to make this operate exceeding several tens of MHz or 100 MHz, the characteristic of the offset voltage etc. is deteriorated.
This is because, the current I1 and a capacitance C of the capacitor C41 determine the through rate of the circuit, so in order to obtain a high speed through rate, it is necessary to make the current I1 as large as possible and make the capacitance C as small as possible.
However, when considering the instant of shift from the sample operation to the hold operation, when turning off the transistor Q46, the transistors Q43 and Q44 almost simultaneously turn off. This is because they operate under substantially the same conditions.
However, the transistors Q41 and Q42 are turned off slightly later due to the effect of the parasitic capacitance etc. As a result, the transistor Q42 turns off later than the transistor Q44. For this reason, an excess charge accumulates in the capacitor C41 from the transistor Q42 and a voltage higher than the inherent output is held.
In order to prevent this from affecting the system, the collector current of the transistor Q45 is used at the time of the hold mode to forcibly lower the emitter voltage of the transistor Q42. The collector current of the transistor Q45 starts to flow slightly earlier than the turning off of the collector current of the transistor Q44. Accordingly, depending on the setting, the transistor Q42 sometimes turns off earlier than the turning off of the transistor Q44.
FIG. 33 is a view explaining the deviation of the held output from the inherent value due to the timing when the transistors Q41 and Q42 are turned off.
This deviation is shorter than one nanosecond (ns) when a device of a cutoff frequency of for example several GHz is used.
However, in the case of a high speed sample-and-hold circuit, the capacitance C must also be lowered to for example about 100 to 300 fF. In such a case, such a slight time difference becomes an offset voltage of several mV or several tens of mV.
Further, the time when the transistors Q42 and Q44 turn off depends upon the difference in characteristics between the npn transistor Q44 and the pnp transistor Q42.
In a usual bipolar IC device, the highest priority is given to the characteristic of the npn transistor. In a so-called "lateral direction pnp" pnp transistor structure, the cutoff frequency is sometimes more than two orders of magnitude lower than that of an npn transistor.
Further, as an option for improving the characteristic of the pnp transistors, there is a bipolar IC device having a vertical direction pnp transistor structure, but in such a device as well, the characteristic of the pnp transistor is generally inferior to the characteristic of the npn transistor.
Accordingly, precise control of the timing of turning off the transistors Q42 and Q44 is very difficult from the viewpoint of the manufacture of the device as well.
Further, if using a device having a high cutoff frequency in order to realize a high speed sample-and-hold characteristic, the "early" voltage determining the output resistance of the transistor is lowered, the inherent gain falls slightly due to the voltage follower, or a yield voltage at the time of an inverse bias between the base and the emitter falls. Accordingly, signals having a large amplitude cannot be handled, and therefore an amplification stage becomes necessary at a stage after the sample-and-hold circuits, the precision of the gain thereof becomes a problem, etc., so the problem arises that it becomes very difficult to suppress the deviation of characteristics among channels as the speed becomes higher.
These problems become conspicuous particularly when the number p of channels is increased. In an image data drive circuit constituted on the same chip, however, matching is still relatively easy.
However, when the number of channels becomes 12 or 24, due to the restrictions of power consumption and the restrictions of the chip size, it becomes necessary to divide the chip into a plurality of chips. Then, it is necessary to consider the case where for example ICs of different manufacturing lots, ICs manufactured at different times, and in an extreme case ICs of different manufacturing lines are combined.
Under such conditions, it is very difficult to keep the deviation among channels small. In the case of a polycrystalline silicon thin film transistor type liquid crystal display panel, there have been many cases where an adjustment step must be inserted in the manufacturing line.